Supported Memories And Transactions; Table 74. Nor Flash/Psram Supported Memories And Transactions - ST STM32F102 Series Reference Manual

RM0008
18.5.2

Supported memories and transactions

Table 74
Transactions not allowed (or not supported) by the FSMC appear in gray.
Table 74.
Device
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
PSRAM
SRAM and
ROM
below displays the supported devices, access modes and transactions.
NOR Flash/PSRAM supported memories and transactions
Mode
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Flexible static memory controller (FSMC)
AHB
Memory
R/W data
data size
size
R 8 16
W 8 16
R 16 16
W 16 16
R 32 16
W 32 16
R - 16
R 8 16
R 16 16
R 32 16
R 8 16
W 8 16
R 16 16
W 16 16
R 32 16
W 32 16
R - 16
R 8 16
R 16 16
R 32 16
8 / 16 /
R 8 / 16
32
8 / 16 /
W 8 / 16
32
Allowed/
not Comments
allowed
Y
N
Y
Y
Split into 2 FSMC
Y
accesses
Split into 2 FSMC
Y
accesses
N Mode is not supported
N
Y
Y
Y
Y Use of byte lanes NBL[1:0]
Y
Y
Split into 2 FSMC
Y
accesses
Split into 2 FSMC
Y
accesses
N Mode is not supported
N
Y
Y
Y Use of byte lanes NBL[1:0]
Y Use of byte lanes NBL[1:0]
373/690