Port Configuration Register High (Gpiox_Crh) (X=A..g - ST STM32F102 Series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
7.2.2

Port configuration register high (GPIOx_CRH) (x=A..G)

Address offset: 0x04
Reset value: 0x4444 4444
31 30 29 28
CNF15[1:0] MODE15[1:0]
rw rw rw
15 14 13 12
CNF11[1:0] MODE11[1:0]
rw rw rw
Bits 31:30, 27:26, 23:22,
19:18, 15:14, 11:10, 7:6, 3:2
Bits 29:28, 25:24, 21:20,
17:16, 13:12, 9:8, 5:4, 1:0
106/690
27 26 25
CNF14[1:0] MODE14[1:0]
rw rw rw rw
11 10 9
CNF10[1:0] MODE10[1:0]
rw rw rw rw
CNFy[1:0]: Port x configuration bits (y= 8 .. 15)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 15: Port bit configuration table on page
In input mode (MODE[1:0]=00):
00: Analog input mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved
In output mode (MODE[1:0]
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
MODEy[1:0]: Port x mode bits (y= 8 .. 15)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 15: Port bit configuration table on page
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.
24 23 22 21
CNF13[1:0] MODE13[1:0]
rw rw rw rw
8 7 6 5
CNF9[1:0] MODE9[1:0]
rw rw rw rw
>
00):
20 19 18 17
CNF12[1:0] MODE12[1:0]
rw rw rw rw
4 3 2 1
CNF8[1:0] MODE8[1:0]
rw rw rw rw
99.
99.
RM0008
16
rw
0
rw