Apb1 Peripheral Reset Register (Rcc_Apb1Rstr) - ST STM32F102 Series Reference Manual

RM0008
Bit 2 IOPARST I/O port A reset
Set and reset by software.
0: No effect
1: Reset I/O port A
Bit 1 Reserved, always read as 0.
Bit 0 AFIORST Alternate function I/O reset
Set and reset by software.
0: No effect
1: Reset Alternate Function
6.3.5

APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
DAC PWR
Reserved
RST RST
Res. rw
15 14 13
SPI3 SPI2
Reserved
RST RST
rw rw Res.
Bits 31:30 Reserved, always read as 0.
Bit 29 DACRST DAC interface reset
Set and reset by software.
0: No effect
1: Reset DAC interface
Bit 28 PWRRST Power interface reset
Set and reset by software.
0: No effect
1: Reset power interface
Bit 27 BKPRST Backup interface reset
Set and reset by software.
0: No effect
1: Reset backup interface
Bit 26 Reserved, always read as 0.
Bit 25 CANRST CAN reset
Set and reset by software.
0: No effect
1: Reset CAN
Bit 24 Reserved, always read as 0.
28 27 26 25
BKP CAN
Res.
RST RST
rw rw Res. rw
12 11 10 9
WWD
GRST
rw
24 23 22
USB I2C2
Res.
RST RST
Res. rw rw
8 7 6
TIM7
Reserved
Res.
Reset and clock control (RCC)
21 20 19 18
UART UART USART
I2C1
5 4 3
RST
RST RST RST
rw rw rw rw
5 4 3 2
TIM6 TIM5 TIM4
RST RST RST RST
rw rw rw rw
17 16
USART
2
Res.
RST
rw res.
1 0
TIM3 TIM2
RST RST
rw rw
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