Status Flags; Error Flags - ST STM32F102 Series Reference Manual

Serial peripheral interface (SPI)
22.4.6

Status flags

Three status flags are provided for the application to fully monitor the state of the I
Busy flag (BSY)
This flag indicates the state of the I
busy communicating and/or that there is a valid data half-word in the Tx buffer awaiting
transmission. The purpose of this flag is to indicate if there is any communication ongoing
2
on the I
1. Data are written into the SPI_DR register in master mode
2. The CK clock is present in slave mode
The Busy flag is reset as soon as a half-word is transmitted/received. It is set and reset by
hardware. This flag can be monitored to avoid write collision errors. Writing to it has no
effect. It is meaningful only when the I2SE bit in the SPI_I2SCFGR register is set.
Tx buffer empty flag (TXE)
When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted
can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to
be transmitted. It is also reset when the I
RX buffer not empty (RXNE)
When set, this flag indicates that there are valid received data in the RX Buffer. It is reset
when SPI_DR register is read.
Channel Side flag (CHSIDE)
In transmission mode, this flag is refreshed when TXE goes high. It indicates the channel
side to which the data to transfer on SD has to belong. In case of an underrun error event in
slave transmission mode, this flag is not reliable and I
switched on before resuming the communication.
In reception mode, this flag is refreshed when data are received into SPI_DR. It indicates
from which channel side data have been received. Note that in case of error (like OVR) this
flag becomes meaningless and the I
(with configuration if it needs changing).
This flag has no meaning in the PCM standard (for both Short and Long frame modes).
When the OVR or UDR flag in the SPI_SR is set and the ERRIE bit in SPI_CR2 is also set,
an interrupt is generated. This interrupt can be cleared by reading the SPI_SR status
register (once the interrupt source has been cleared).
22.4.7

Error flags

There are two error flags for the I
Underrun flag (UDR)
In slave transmission mode this flag is set when the first clock for data transmission appears
while the software has not yet loaded any value into SPI_DR. It is available when the
I2SMOD bit in SPI_I2SCFGR is set. An interrupt may be generated if the ERRIE bit in
SPI_CR2 is set.
The UDR bit is cleared by a read operation on the SPI_SR register.
568/690
S bus or not. This flag becomes set as soon as:
2
S communication layer. It is set to indicate that the I
2
S is disabled (I2SE bit is reset).
2
2
S should be reset by disabling and then enabling it
2
S cell.
S needs to be switched off and
RM0008
2
S bus.
2
S is