ST STM32F102 Series Reference Manual page 118

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Bit 15 PD01_REMAP Port D0/Port D1 mapping on OSC_IN/OSC_OUT
This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality.
When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can
be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48- and 64-pin packages
(PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).
0: No remapping of PD0 and PD1
1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,
Bits 14:13 CAN_REMAP[1:0] CAN alternate function remapping
These bits are set and cleared by software. They control the mapping of Alternate Functions
CANRX and CANTX.
00: CANRX mapped to PA11, CANTX mapped to PA12
01: Not used
10: CANRX mapped to PB8, CANTX mapped to PB9 (not available on 36-pin package)
11: CANRX mapped to PD0, CANTX mapped to PD1
Bit 12 TIM4_REMAP TIM4 remapping
This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the
GPIO ports.
0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
Note: TIM4_ETR on PE0 is not re-mapped.
Bits 11:10 TIM3_REMAP[1:0] TIM3 remapping
These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on
the GPIO ports.
00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
01: Not used
10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
Note: TIM3_ETR on PE0 is not re-mapped.
Bits 9:8 TIM2_REMAP[1:0] TIM2 remapping
These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and
external trigger (ETR) on the GPIO ports.
00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
Bits 7:6 TIM1_REMAP[1:0] TIM1 remapping
These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4, 1N
to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.
00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13,
CH2N/PB14, CH3N/PB15)
01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7,
CH2N/PB0, CH3N/PB1)
10: not used
11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,
CH2N/PE10, CH3N/PE12)
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