ST STM32F102 Series Reference Manual page 603

RM0008
Bit 10 AF: Acknowledge Failure.
0: No acknowledge failure
1: Acknowledge failure
– Set by hardware when no acknowledge is returned.
– Cleared by software writing 0, or by hardware when PE=0.
Bit 9 ARLO: Arbitration Lost (master mode)
0: No Arbitration Lost detected
1: Arbitration Lost detected
Set by hardware when the interface loses the arbitration of the bus to another master
– Cleared by software writing 0, or by hardware when PE=0.
After an ARLO event the interface switches back automatically to Slave mode (M/SL=0).
Note:
In SMBUS, the arbitration on the data in slave mode occurs only during the data phase, or the
acknowledge transmission (not on the address acknowledge).
Bit 8 BERR: Bus Error
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
– Set by hardware when the interface detects a misplaced Start or Stop condition
– Cleared by software writing 0, or by hardware when PE=0.
Bit 7 TxE: Data Register Empty (transmitters)
0: Data register not empty
1: Data register empty
– Set when DR is empty in transmission. TxE is not set during address phase.
– Cleared by software writing to the DR register or by hardware after a start or a stop condition or
when PE=0.
TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)
Bit 6 RxNE: Data Register not Empty (receivers).
0: Data register empty
1: Data register not empty
– Set when data register is not empty in receiver mode. RxNE is not set during address phase.
– Cleared by software reading or writing the DR register or by hardware when PE=0.
RxNE is not set in case of ARLO event.
Bit 5 Reserved, forced by hardware to 0.
Bit 4 STOPF: Stop detection (Slave mode)
0: No Stop condition detected
1: Stop condition detected
– Set by hardware when a Stop condition is detected on the bus by the slave after an acknowledge
(if ACK=1).
– Cleared by software reading the SR1 register followed by a write in the CR1 register, or by
hardware when PE=0
Note:
The STOPF bit is not set after a NACK reception
Inter-integrated circuit (I
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C) interface
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