R1B; R2 (Cid, Csd Register); R3 (Ocr Register); Table 124. R1 Response - ST STM32F102 Series Reference Manual

RM0008

Table 124. R1 response

Bit position
47
46
[45:40]
[39:8]
[7:1]
0
19.5.2

R1b

It is identical to R1 with an optional busy signal transmitted on the data line. The card may
become busy after receiving these commands based on its state prior to the command
reception.
19.5.3

R2 (CID, CSD register)

Code length = 136 bits. The contents of the CID register are sent as a response to the
CMD2 and CMD10 commands. The contents of the CSD register are sent as a response to
CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of
these registers is replaced by the end bit of the response. The card indicates that an erase
is in progress by holding MCDAT low. The actual erase time may be quite long, and the host
may issue CMD7 to deselect the card.

Table 125. R2 response

Bit position
135
134
[133:128]
[127:1]
0
19.5.4

R3 (OCR register)

Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1.
The level coding is as follows: restricted voltage windows = low, card busy = low.
Width (bits
1 0
1 0
6 X
32 X
7 X
1 1
Width (bits
1 0
1 0
6 '111111'
127 X
1 1
SDIO interface (SDIO)
Value
Start bit
Transmission bit
Command index
Card status
CRC7
End bit
Value
Start bit
Transmission bit
Command index
Card status
End bit
Description
Description
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