Own Address Register 2 (I2C_Oar2); Data Register (I2C_Dr) - ST STM32F102 Series Reference Manual

RM0008
23.6.4

Own address register 2 (I2C_OAR2)

Address offset: 0x0C
Reset value: 0x0000
15 14 13 12
Reserved
Bits 15:8 Reserved, forced by hardware to 0.
Bits 7:1 ADD2[7:1]: Interface address
bits 7:1 of address in dual addressing mode
Bit 0 ENDUAL: Dual addressing mode enable
0: Only OAR1 is recognized in 7-bit addressing mode
1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode
23.6.5

Data register (I2C_DR)

Address offset: 0x10
Reset value: 0x0000
15 14 13 12
Reserved
Bits 15:8 Reserved, forced by hardware to 0.
Bits 7:0 DR[7:0] 8-bit Data Register
Byte received or to be transmitted to the bus.
– Transmitter mode: Byte transmission starts automatically when a byte is written in the DR register.
A continuous transmit stream can be maintained if the next data to be transmitted is put in DR
once the transmission is started (TxE=1)
– Receiver mode: Received byte is copied into DR (RxNE=1). The received data in the DR register
must be read before the next data reception, otherwise an overrun occurs and the last byte will be
lost.
1. In slave mode, the address is not copied into DR.
2. Write collision is not managed (DR can be written if TxE=0).
3. If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so cannot be read.
11 10 9
Res.
11 10 9
Res.
(1)(2)(3)
Inter-integrated circuit (I
8 7 6 5
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8 7 6 5
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4 3 2
ADD2[7:1]
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4 3 2
DR[7:0]
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2
C) interface
1 0
ENDUAL
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1 0
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