Dma Requests - ST STM32F102 Series Reference Manual

RM0008
How to use the interface in SMBus mode
To switch from I
●
Set the SMBus bit in the I2C_CR1 register
●
Configure the SMBTYPE and ENARP bits in the I2C_CR1 register as required for the
application
If you want to configure the device as a master, follow the Start condition generation
procedure in
Section 23.3.2: I2C slave
The application has to control the various SMBus protocols by software.
●
SMB Device Default Address acknowledged if ENARP=1 and SMBTYPE=0
●
SMB Host Header acknowledged if ENARP=1 and SMBTYPE=1
●
SMB Alert Response Address acknowledged if SMBALERT=1
23.3.7

DMA requests

DMA requests (when enabled) are generated only for data transfer. DMA requests are
generated by Data Register becoming empty in transmission and Data Register becoming
full in reception. When the number of data transfers which has been programmed for the
corresponding DMA channel is reached, the DMA controller sends an End of Transfer EOT
signal to the I
●
Master Transmitter: In the interrupt routine after the EOT interrupt, disable DMA
requests then wait for a BTF event before programming the Stop condition.
●
Master Receiver: The DMA controller sends a hardware signal EOT_1 corresponding
to the (number of bytes -1). If, in the I2C_CR2 register, the LAST bit is set, I
automatically sends a NACK after the next byte following EOT_1. The user can
generate a Stop condition in the DMA Transfer Complete interrupt routine if enabled.
Note: Please refer to the product specs for availability DMA controller. If DMA is not available in
the product, the user should use I
clear TxE/ RxNE flags to achieve continuous communication.
Transmission using DMA
DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2
register. Data will be loaded from a Memory area configured using the DMA peripheral (refer
to the DMA specification) to the I2C_DR register whenever the TxE bit is set. To map a DMA
channel for I
2
C mode to SMBus mode, the following sequence should be performed.
Section 23.3.3: I2C master
mode.
2
C interface and generates a Transfer Complete interrupt if enabled:
2
C transmission, perform the following sequence. Here x is the channel number.
1. Set the I2C_DR register address in the DMA_CPARx register. The data will
be moved to this address from the memory after each TxE event.
2. Set the memory address in the DMA_CMARx register. The data will be
loaded into I2C_DR from this memory after each TxE event.
3. Configure the total number of bytes to be transferred in the DMA_CNDTRx
register. After each TxE event, this value will be decremented.
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx
register
5. Set the DIR bit and, in the DMA_CCRx register, configure interrupts after half
transfer or full transfer depending on application requirements.
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
Inter-integrated circuit (I
mode. Otherwise, follow the sequence in
2
C as explained in section 1.4. In the I
2
C) interface
2
C
2
C ISR, the user can
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