Dma Address For Full Transfer (Timx_Dmar); Tim1&Tim8 Register Map; Table 56. Tim1&Tim8 Register Map And Reset Values - ST STM32F102 Series Reference Manual

RM0008
12.4.20

DMA address for full transfer (TIMx_DMAR)

Address offset: 0x4C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 DMAB[15:0]: DMA register for burst accesses.
A read or write access to the DMAR register accesses the register located at the address:
"(TIMx_CR1 address) + DBA + (DMA index)" in which:
TIMx_CR1 address is the address of the control register 1,
DBA is the DMA base address configured in TIMx_DCR register,
DMA index is the offset automatically controlled by the DMA transfer, depending on the length of the
transfer DBL in the TIMx_DCR register.
12.4.21 TIM1&TIM8 register map
TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table
below:
Table 56. TIM1&TIM8 Register map and reset values
Offset Register
TIMx_CR1
0x00
Reset value
TIMx_CR2
0x04
Reset value
TIMx_SMCR
0x08
Reset value
TIMx_DIER
0x0C
Reset value
TIMx_SR
0x10
Reset value
TIMx_EGR
0x14
Reset value
TIMx_CCMR1
Output Compare
mode
Reset value
0x18
TIMx_CCMR1
Input Capture
mode
Reset value
12 11 10 9
rw rw rw rw
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Advanced-control timers (TIM1&TIM8)
8 7 6
DMAB[15:0]
rw rw rw
Reserved
0
0 0
0
Reserved
OC2M
0 0
IC2F[3:0]
0 0
5 4 3 2
rw rw rw rw
CKD CMS
[1:0] [1:0]
0 0 0 0
MMS[2:0]
0 0 0 0 0 0 0 0
ETPS
ETF[3:0] TS[2:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0
CC2S OC1M
[2:0] [1:0] [2:0]
0 0 0 0 0 0 0 0
IC2
CC2S
PSC IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0
1 0
rw rw
0 0 0 0 0 0
0 0 0 0 0
SMS[2:0]
0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
CC1S
[1:0]
0 0 0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0 0 0
271/690