Rtc Prescaler Divider Register (Rtc_Divh / Rtc_Divl) - ST STM32F102 Series Reference Manual

Real-time clock (RTC)
RTC prescaler load register low (RTC_PRLL)
Address offset: 0x0C
Write only (see
Reset value: 0x8000
15 14 13
w w w
Bits 15:0 PRL[15:0]: RTC Prescaler Reload Value Low
These bits are used to define the counter clock frequency according to the following formula:
f = f
TR_CLK
Note: If the input clock frequency (f
signal period of 1 second.
15.4.4

RTC prescaler divider register (RTC_DIVH / RTC_DIVL)

During each period of TR_CLK, the counter inside the RTC prescaler is reloaded with the
value stored in the RTC_PRL register. To get an accurate time measurement it is possible to
read the current value of the prescaler counter, stored in the RTC_DIV register, without
stopping it. This register is read-only and it is reloaded by hardware after any change in the
RTC_PRL or RTC_CNT registers.
RTC prescaler divider register high (RTC_DIVH)
Address offset: 0x10
Reset value: 0x0000
15 14 13
Bits 15:4 Reserved
Bits 3:0 RTC_DIV[19:16]: RTC Clock Divider High
RTC prescaler divider register low (RTC_DIVL)
Address offset: 0x14
Reset value: 0x8000
15 14 13
r r r
Bits 15:0 RTC_DIV[15:0]: RTC Clock Divider Low
350/690
Section 15.3.4 on page
12 11 10 9
w w w w
/(PRL[19:0]+1)
RTCCLK
RTCCLK
12 11 10 9
Reserved
12 11 10 9
r r r r
345)
8 7 6 5
PRL[15:0]
w w w w
) is 32.768 kHz, write 7FFFh in this register to get a
8 7 6 5
8 7 6 5
RTC_DIV[15:0]
r r r r
RM0008
4 3 2 1
w w w w
4 3 2 1
RTC_DIV[19:16]
r r r
4 3 2 1
r r r r
0
w
0
r
0
r