ST STM32F102 Series Reference Manual page 577

RM0008
Bit 7 PCMSYNC: PCM frame synchronization
0: Short frame synchronization
1: Long frame synchronization
Notes: This bit has a meaning only if I2SSTD = 11 (PCM standard is used)
Not used for the SPI mode
Bit 6 Reserved: forced at 0 by hardware
Bit 5:4 I2SSTD: I
2
00: I S Phillips standard.
01: MSB justified standard (left justified)
10: LSB justified standard (right justified)
11: PCM standard
For more details on I
Notes: For correct operation, these bits should be configured when the I
Not used in SPI mode
Bit 3 CKPOL: steady state clock polarity
2
0: I S clock steady state is low level
2
1: I S clock steady state is high level
Notes: For correct operation, this bit should be configured when the I
Not used in SPI mode
Bit 2:1 DATLEN: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Notes: For correct operation, these bits should be configured when the I
Not used in SPI mode
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in.
Notes: For correct operation, this bit should be configured when the I
Not used in SPI mode
2
S standard selection
2
S standards, refer to
Serial peripheral interface (SPI)
Section 22.4.2 on page 557
2
S is disabled.
2
S is disabled.
2
S is disabled.
2
S is disabled.
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