ST STM32F102 Series Reference Manual page 598

Inter-integrated circuit (I
Bit 8 START: Start Generation
This bit is set and cleared by software and cleared by hardware when start is sent or PE=0.
In Master Mode:
0: No Start generation
1: Repeated start generation
In Slave mode:
0: No Start generation
1: Start generation when the bus is free
Bit 7 NOSTRETCH: Clock Stretching Disable (Slave mode)
This bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until it is reset
by software.
0: Clock stretching enabled
1: Clock stretching disabled
Bit 6 ENGC: General Call Enable
0: General call disabled. Address 00h is NACKed.
1: General call enabled. Address 00h is ACKed.
Bit 5 ENPEC: PEC Enable
0: PEC calculation disabled
1: PEC calculation enabled
Bit 4 ENARP: ARP Enable
0: ARP disable
1: ARP enable
SMBus Device default address recognized if SMBTYPE=0
SMBus Host address recognized if SMBTYPE=1
Bit 3 SMBTYPE: SMBus Type
0: SMBus Device
1: SMBus Host
Bit 2 Reserved, forced by hardware to 0.
Bit 1 SMBUS: SMBus Mode
2
0: I C mode
1: SMBus mode
Bit 0 PE: Peripheral Enable
0: Peripheral disable
1: Peripheral enable: the corresponding I/Os are selected as alternate functions depending on SMBus
bit.
Note:
If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current
communication, when back to IDLE state.
All bit resets due to PE=0 occur at the end of the communication.
In master mode, this bit must not be reset before the end of the communication.
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C) interface RM0008