Sw-Dp State Machine (Reset, Idle States, Id Code); Table 162. Packet Request (8-Bits); Table 163. Ack Response (3 Bits); Table 164. Data Transfer (33 Bits) - ST STM32F102 Series Reference Manual

RM0008

Table 162. Packet request (8-bits)

Bit
0
1
2
4:3
5
6
7
Refer to the Cortex-M3 r1p1 TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.

Table 163. ACK response (3 bits)

Bit
0..2
The ACK Response must be followed by a turnaround time only if it is a READ transaction or
if a WAIT or FAULT acknowledge has been received.

Table 164. DATA transfer (33 bits)

Bit
0..31
32
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.
26.8.3

SW-DP state machine (Reset, idle states, ID code)

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default ARM one and is set at
0x1BA01477 (corresponding to Cortex-M3 r1p1).
Name
Start Must be "1"
0: DP Access
APnDP
1: AP Access
0: Write Request
RnW
1: Read Request
A(3:2) Address field of the DP or AP registers (refer to
Parity Single bit parity of preceding bits
Stop 0
Not driven by the host. Must be read as "1" by the target
Park
because of the pull-up
Name
001: FAULT
ACK
010: WAIT
100: OK
Name
WDATA or
Write or Read data
RDATA
Parity
Single parity of the 32 data bits
Debug support (DBG)
Description
Table
Description
Description
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