Figure 47. Advanced-Control Timer Block Diagram - ST STM32F102 Series Reference Manual

Advanced-control timers (TIM1&TIM8)

Figure 47. Advanced-control timer block diagram

TIMx_ETR
TI1
XOR
TIMx_CH1
TI2
TIMx_CH2
TI3
TIMx_CH3
TI4
TIMx_CH4
BRK
TIMx_BKIN
Clock failure event from clock controller
208/690
Internal Clock (CK_INT)
CK_TIM18 from RCC
ETR
Polarity Selection & Edge
Detector & Prescaler
ITR0
ITR1
ITR2
ITR3
CK_PSC
TI1FP1
IC1
Input Filter &
TI1FP2
Edge detector
TRC
IC2
TI2FP1
Input Filter &
TI2FP2
Edge detector
TRC
TI3FP3
IC3
Input Filter &
TI3FP4
Edge detector
TRC
TI4FP3 IC4
Input Filter &
TI4FP4
Edge detector
TRC
Polarity Selection
CSS (Clock Security system
ETRF
ETRP
Input Filter
TGI
ITR
TRC
TRGI
TI1F_ED
TI1FP1
TI2FP2
U
AutoReload Register
Stop, Clear Up/Down
or
PSC CNT
CK_CNT
+/-
Prescaler COUNTER
CC1I
U
IC1PS
Prescaler Capture/Compare 1 Register
CC2I
U
IC2PS
Prescaler
Capture/Compare 2 Register
CC3I
U
IC3PS
Prescaler Capture/Compare 3 Register
CC4I
U
IC4PS
Prescaler
Capture/Compare 4 Register
ETRF
BI
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
event
interrupt & DMA output
Trigger
Controller
TRGO
to other timers
to DAC/ADC
Slave
Reset, Enable, Up/Down, Count
Mode
Controller
Encoder
Interface
REP Register
UI
Repetition
U
counter
DTG registers
CC1I
OC1REF
output
DTG
control
CC2I
OC2REF output
DTG
control
CC3I
OC3REF
output
DTG
control
CC4I
OC4REF
output
control
RM0008
TIMx_CH1
OC1
TIMx_CH1N
OC1N
TIMx_CH2
OC2
TIMx_CH2N
OC2N
TIMx_CH3
OC3
TIMx_CH3N
OC3N
TIMx_CH4
OC4