Backup Control Register (Bkp_Cr) - ST STM32F102 Series Reference Manual

Backup registers (BKP)
Bit 8 ASOE Alarm or Second Output Enable
Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the
TAMPER pin depending on the ASOS bit.
The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the
ASOE bit is set.
Note: This bit is reset only by a Backup domain reset.
Bit 7 CCO Calibration Clock Output
0: No effect
1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin. The
TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted Tamper
detection.
Note: This bit is reset when the V
Bit 6:0 CAL[6:0] Calibration value
This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses. This
allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20 PPM.
The clock of the RTC can be slowed down from 0 to 121PPM.
5.4.3

Backup control register (BKP_CR)

Address offset: 0x30
Reset value: 0x0000 0000
14 13
15
Bits 15:2 Reserved, always read as 0.
Bit 1 TPAL TAMPER pin active level
0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set).
1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set).
Bit 0 TPE TAMPER pin enable
0: The TAMPER pin is free for general purpose I/O
1: Tamper alternate I/O function is activated.
Note: Setting the TPAL and TPE bits at the same time is always safe, however resetting both at
the same time can generate a spurious Tamper event. For this reason it is recommended to
change the TPAL bit only when the TPE bit is reset.
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DD
12 11 10 9
Reserved
supply is powered off.
8 7 6
Res.
5 4 3 2
RM0008
1
0
TPAL TPE
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