Figure 145. Counter Timing Diagram, Internal Clock Divided By 2; Figure 146. Counter Timing Diagram, Internal Clock Divided By 4; Figure 147. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F102 Series Reference Manual

Basic timer (TIM6&7)

Figure 145. Counter timing diagram, internal clock divided by 2

Figure 146. Counter timing diagram, internal clock divided by 4

Figure 147. Counter timing diagram, internal clock divided by N

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CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
0034
0035 0036 0000 0001 0002 0003
0035 0036
1F 20
RM0008
0000 0001
00