Adc Injected Data Register X (Adc_Jdrx) (X= 1; Adc Regular Data Register (Adc_Dr) - ST STM32F102 Series Reference Manual

RM0008

10.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)

Address offset: 0x3C - 0x48
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
r r r
Bits 31:16 Reserved, must be kept cleared.
Bits 15:0 JDATA[15:0]: Injected data
These bits are read only. They contain the conversion result from injected channel x. The data is left
or right-aligned as shown in

10.12.14 ADC regular data register (ADC_DR)

Address offset: 0x4C
Reset value: 0x0000 0000
31 30 29 28
r r r
15 14 13 12
r r r
Bits 31:16 ADC2DATA[15:0]: ADC2 data
– In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to
ADC mode
– In ADC2 and ADC3: these bits are not used
Bits 15:0 DATA[15:0]: Regular data
These bits are read only. They contain the conversion result from the regular channels. The data is
left or right-aligned as shown in
27 26 25
11 10 9
r r r r
Figure 26
27 26 25
r r r r
11 10 9
r r r r
Figure 26
24 23 22 21
Reserved
8 7 6 5
JDATA[15:0]
r r r r
and Figure 27.
24 23 22 21
ADC2DATA[15:0]
r r r r
8 7 6 5
DATA[15:0]
r r r r
and Figure 27.
Analog-to-digital converter (ADC)
20 19 18
4 3 2
r r r
20 19 18
r r r
4 3 2
r r r
Section 10.9: Dual
17 16
1 0
r r
17 16
r r
1 0
r r
181/690