Control Register 2 (Timx_Cr2); Dma/Interrupt Enable Register (Timx_Dier) - ST STM32F102 Series Reference Manual

Basic timer (TIM6&7)
14.4.2

Control register 2 (TIMx_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13
Bits 15:7 Reserved, always read as 0.
Bits 6:4 MMS: Master Mode Selection.
These bits are used to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is
generated by the trigger input (slave mode controller configured in reset mode) then the signal on
TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful
to start several timers at the same time or to control a window in which a slave timer is enabled. The
Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input
when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except
if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).
010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer
can then be used as a prescaler for a slave timer.
Bits 3:0 Reserved, always read as 0
14.4.3

DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Reserved
Res.
Bit 15:9 Reserved, always read as 0.
Bit 8 UDE: Update DMA request enable.
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7:1 Reserved, always read as 0.
Bit 0 UIE: Update interrupt enable.
0: Update interrupt disabled.
1: Update interrupt enabled.
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12 11 10 9
Reserved
Res.
12 11 10 9
8 7 6 5
MMS[2:0]
rw rw
8 7 6 5
UDE
rw
4 3 2
Reserved
rw Res.
4 3 2
Reserved
Res.
RM0008
1 0
1 0
UIE
rw