Hardware Watchdog; Register Access Protection; Debug Mode; Table 63. Watchdog Timeout Period (With 40 Khz Input Clock) - ST STM32F102 Series Reference Manual

RM0008
16.3.1

Hardware watchdog

If the "Hardware watchdog" feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and will generate a reset unless the Key register is
written by the software before the counter reaches end of count.
16.3.2

Register access protection

Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you
must first write the code 0x5555 in the IWDG_KR register. A write access to this register
with a different value will break the sequence and register access will be protected again.
This implies that it is the case of the reload operation (writing 0xAAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
16.3.3

Debug mode

When the microcontroller enters debug mode (Cortex-M3 core halted), the IWDG counter
either continues to work normally or stops, depending on DBG_IWDG_STOP configuration
bit in DBG module. For more details, refer to
watchdog, bxCAN and

Figure 154. Independent watchdog block diagram

1.8 V voltage domain
Prescaler Register
IWDG_PR
LSI
(40 kHz)
VDD voltage domain
Note: The watchdog function is implemented in the V
Stop and Standby modes.
Table 63.
Prescaler divider
1. These timings are given for a 40 kHz clock but the microcontroller's internal RC frequency can vary from
30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the
phasing of the APB interface clock versus the RC oscillator 40 kHz clock so that there is always a full RC
period of uncertainty.
I2C.
Status Register
IWDG_SR
8-bit
Prescaler
Watchdog timeout period (with 40 kHz input clock)
/4
/8
/16
/32
/64
/128
/256
Section 26.15.2: Debug support for timers,
Reload Register
IWDG_RLR
12-bit reload value
12-bit Down-counter
voltage domain that is still functional in
DD
Min timeout (ms)
PR[2:0] bits
RL[11:0]= 0x000
0
1
2
3
4
5
6 (or 7)
Independent watchdog (IWDG)
Key Register
IWDG_KR
IWDG RESET
(1)
Max timeout (ms)
RL[11:0]= 0xFFF
0.1
0.2
0.4 1638.4
0.8 3276.8
1.6 6553.6
3.2 13107.2
6.4 26214.4
409.6
819.2
355/690