Can Registers; Register Access Protection; Can Control And Status Registers - ST STM32F102 Series Reference Manual

Controller area network (bxCAN)
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The error and status change interrupt can be generated by the following events:
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21.6

CAN registers

21.6.1

Register access protection

Erroneous access to certain configuration registers can cause the hardware to temporarily
disturb the whole CAN network. Therefore the CAN_BTR register can be modified by
software only while the CAN hardware is in initialization mode.
Although the transmission of incorrect data will not cause problems at the CAN network
level, it can severely disturb the application. A transmit mailbox can be only modified by
software while it is in empty state, refer to
The filters values can be modified either deactivating the associated filter banks or by setting
the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO
assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when
the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
21.6.2

CAN control and status registers

Refer to
CAN master control register (CAN_MCR)
Address offset: 0x00
Reset value: 0x0001 0002
31 30 29
15 14 13
RE
SET
rs
Bits 31:16 Reserved, forced by hardware to 0.
Bit 15 RESET: bxCAN software master reset
0: Normal operation.
1: Force a master reset of the bxCAN -> Sleep mode activated after reset (FMP bits and
CAN_MCR register are initialized to the reset values). This bit is automatically reset to 0.
Bits 14:8 Reserved, forced by hardware to 0.
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Error condition, for more details on error conditions please refer to the CAN Error
Status register (CAN_ESR).
Wakeup condition, SOF monitored on the CAN Rx signal.
Entry into Sleep mode.
Section 1.1 on page 32
28 27 26 25
12 11 10 9
Reserved
Res.
Figure 197: Transmit mailbox
for a list of abbreviations used in register descriptions.
24 23 22
Reserved
8 7 6
TTCM ABOM AWUM
rw rw
states.
21 20 19 18
5 4 3 2
NART RFLM TXFP
rw rw rw rw
RM0008
17 16
1 0
SLEEP INRQ
rw rw