Dma Channel X Configuration Register (Dma_Ccrx) (X = 1 - ST STM32F102 Series Reference Manual

DMA controller (DMA)
9.4.3

DMA channel x configuration register (DMA_CCRx) (x = 1 ..7)

Address offset: 0x08 + 20d × Channel number
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
MEM2
PL[1:0]
MEM
Res.
rw rw
Bits 31:15 Reserved, always read as 0.
Bit 14 MEM2MEM: Memory to memory mode
This bit is set and cleared by software.
0: Memory to memory mode disabled
1: Memory to memory mode enabled
Bits 13:12 PL[1:0]: Channel Priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
Bits 11:10 MSIZE[1:0]: Memory size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bits 9:8 PSIZE[1:0]: Peripheral size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bit 7 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory increment mode disabled
1: Memory increment mode enabled
Bit 6 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral increment mode disabled
1: Peripheral increment mode enabled
Bit 5 CIRC: Circular mode
This bit is set and cleared by software.
0: Circular mode disabled
1: Circular mode enabled
144/690
27 26 25
11 10 9
MSIZE[1:0] PSIZE[1:0]
rw rw rw rw
24 23 22 21
Reserved
8 7 6 5
MINC PINC CIRC
rw rw rw rw
20 19 18 17
4 3 2 1
DIR TEIE HTIE TCIE
rw rw rw rw
RM0008
16
0
EN
rw