Counter (Timx_Cnt); Prescaler (Timx_Psc); Auto-Reload Register (Timx_Arr) - ST STM32F102 Series Reference Manual

Advanced-control timers (TIM1&TIM8)
12.4.10

Counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000
15 14 13
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Bits 15:0 CNT[15:0]: Counter Value.
12.4.11

Prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
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Bits 15:0 PSC[15:0]: Prescaler Value.
The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event (including
when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when
configured in "reset mode").
12.4.12

Auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0x0000
15 14 13
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Bits 15:0 ARR[15:0]: Prescaler Value.
ARR is the value to be loaded in the actual auto-reload register.
Refer to the
behavior.
The counter is blocked while the auto-reload value is null.
264/690
12 11 10 9
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12 11 10 9
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12 11 10 9
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Section 12.3.1: Time-base unit on page 209
8 7 6 5
CNT[15:0]
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8 7 6 5
PSC[15:0]
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/ (PSC[15:0] + 1).
CK_PSC
8 7 6 5
ARR[15:0]
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for more details about ARR update and
4 3 2 1
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4 3 2 1
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4 3 2 1
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RM0008
0
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0
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0
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