Table 174. Document Revision History; Figure 76. Output Stage Of Capture/Compare Channel (Channel 4) - ST STM32F102 Series Reference Manual

Revision history
27 Revision history

Table 174. Document revision history

Date
19-Oct-2007
680/690
Revision
Document reference number changed from UM0306 to RM008. The
changes below were made with reference to revision 1 of 01-Jun-2007 of
UM0306.
EXTSEL[2:0] and JEXTSEL[2:0] removed from
page 151 and V
Notes added to
Section 10.9.7 on page 165
SPI_CR2 corrected to SPI_CR1 in
page 551.
f frequency changed to f
CPU
on page 544.
Section 22.3.6: CRC calculation on page 552
communication using DMA (direct memory addressing) on page 553
modified.
Note added to bit 13 description changed in
Register 1 (SPI_CR1) (not used in I
modified in Section 22.5.3: SPI status register (SPI_SR) on page
On 64-pin packages on page 49
Section 7.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 on
page 110 updated.
Description of SRAM at address 0x4000 6000 modified in
map on page 35
Note added to
Section 21.2: bxCAN main features on page
1
Figure 4: Power supply overview
modified.
Formula added to Bits 25:24 description in
(CAN_BTR) on page
Section 9.3: DMA functional description on page 135
Example of configuration on page 670
MODEx[1:0] bit definitions corrected in
register high (GPIOx_CRH) (x=A..G) on page
Downcounting mode on page 213
Figure 76: Output stage of capture/compare channel (channel 4) on
page 224 and
OCx output enable conditions modified in
page 228.
Section 12.3.19: TIMx and external trigger synchronization on page 243
changed.
CC1S, CC2S, CC3S and CC4S definitions modified for (1, 1) bit setting
modified in Section 12.4.7: Capture/compare mode register 1
(TIMx_CCMR1)
(TIMx_CCMR2).
CC1S, CC2S, CC3S and CC4S definitions for (1, 1) bit setting modified in
Section 13.4.7: Capture/compare mode register 1 (TIMx_CCMR1)
Section 13.4.8: Capture/compare mode register 2
AFIO_EVCR pins modified in
on page 122.
Changes
range modified in Remarks column.
REF+
Section 10.3.9 on page
and Section 10.9.9 on page
1 clock and 1 bidirectional data wire on
in Section 22.2: SPI and I
PCLK
2
S mode) on page
modified.
and Table 1: Register boundary
Section 20.2: USB main features on page 468
and On 100-pin and 144- pin packages
527.
modified.
Figure 78: Output compare mode, toggle on OC1.
and Section 12.4.8: Capture/compare mode register 2
Table 35: AFIO register map and reset values
Section 12.3.6: Input capture mode on page 224
Table 42: ADC pins on
154, Section 10.9.2 on page
166.
2
S main features
and Section 22.3.7: SPI
Section 22.5.1: SPI Control
569. Note for bit 4
Figure 2: Memory
addresses.
and
499.
CAN bit timing register
modified.
modified.
Section 7.2.2: Port configuration
106.
Section 12.3.10: PWM mode on
(TIMx_CCMR2).
RM0008
162,
573.
modified.
title
and
modified.