I 2 C Functional Description; Mode Selection - ST STM32F102 Series Reference Manual

RM0008
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2 Interrupt vectors:
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● Optional Clock Stretching
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1-byte buffer with DMA capability
● Configurable PEC (Packet Error Checking) Generation or Verification:
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SMBus 2.0 Compatibility:
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PMBus Compatibility
Note: Some of the above features may not be available in certain products. The user should refer
to the product data sheet, to identify the specific features supported by the I
implementation.
2
23.3 I C functional description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
with a standard (up to 100 kHz) or fast (up to 400 kHz) I
23.3.1

Mode selection

The interface can operate in one of the four following modes:
●
Slave transmitter
●
Slave receiver
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Master transmitter
●
Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master, after it generates a START condition and from master to slave, if an arbitration loss
or a Stop generation occurs, allowing multimaster capability.
Communication flow
In Master mode, the I
serial data transfer always begins with a start condition and ends with a stop condition. Both
start and stop conditions are generated in master mode by software.
Acknowledgement failure after address/ data transmission
Detection of misplaced start or stop condition
Overrun/Underrun if clock stretching is disabled
1 Interrupt for successful address/ data communication
1 Interrupt for error condition
PEC value can be transmitted as last byte in Tx mode
PEC error checking for last received byte
25 ms clock low timeout delay
10 ms master cumulative clock low extend time
25 ms slave cumulative clock low extend time
Hardware PEC generation/verification with ACK control
Address Resolution Protocol (ARP) supported
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
2
C interface initiates a data transfer and generates the clock signal. A
Inter-integrated circuit (I
2
C bus.
2
C) interface
2
C interface
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