Jtag Debug Port; Table 160. Jtag Debug Port Data Registers - ST STM32F102 Series Reference Manual

RM0008
26.7

JTAG debug port

A standard JTAG state machine is implemented with a 4-bit Instruction Register (IR) and five
Data Registers (for full details, refer to the Cortex-M3 r1p1 Technical Reference Manual
(TRM):

Table 160. JTAG debug port data registers

IR(3:0)
1111
1110
1010
1011
1000
Data register
BYPASS
[1 bit]
IDCODE ID CODE
[32 bits] 0x3BA00477 (ARM Cortex-M3 r1p1 ID Code)
Debug Port Access Register
This initiates a debug port and allows access to a debug port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request
Bits 2:1 = A[3:2] = 2-bit address of a debug port register.
Bit 0 = RnW = Read request (1) or write request (0).
DPACC
– When transferring data OUT:
[35 bits]
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
Refer to
Access Port Access Register
Initiates an access port and allows access to an access port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request
Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).
Bit 0 = RnW= Read request (1) or write request (0).
– When transferring data OUT:
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
APACC
request
[35 bits]
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
There are many AP Registers (see AHB-AP) addressed as the
combination of:
– The shifted value A[3:2]
– The current value of the DP SELECT register
Abort Register
ABORT
– Bits 31:1 = Reserved
[35 bits]
– Bit 0 = DAPABORT: write 1 to generate a DAP abort.
Table 161 for a description of the A(3:2) bits
Debug support (DBG)
Details
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