Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A..g; Port Bit Reset Register (Gpiox_Brr) (X=A..g - ST STM32F102 Series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
7.2.5

Port bit set/reset register (GPIOx_BSRR) (x=A..G)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
BR15 BR14 BR13 BR12
w w w
15 14 13
BS15 BS14 BS13
w w w
Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Set the corresponding ODRx bit
7.2.6

Port bit reset register (GPIOx_BRR) (x=A..G)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
15 14 13
BR15 BR14 BR13 BR12
w w w
Bits 31:16 Reserved
Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
108/690
28 27 26 25
BR11 BR10 BR9
w w w w
12 11 10 9
BS12 BS11 BS10 BS9
w w w w
28 27 26 25
12 11 10 9
BR11 BR10 BR9
w w w w
24 23 22 21
BR8 BR7 BR6 BR5
w w w w
8 7 6 5
BS8 BS7 BS6 BS5
w w w w
24 23 22 21
Reserved
8 7 6 5
BR8 BR7 BR6 BR5
w w w w
20 19 18 17
BR4 BR3 BR2 BR1
w w w w
4 3 2 1
BS4 BS3 BS2 BS1
w w w w
20 19 18 17
4 3 2 1
BR4 BR3 BR2 BR1
w w w w
RM0008
16
BR0
w
0
BS0
w
16
0
BR0
w