Bxcan Register Map; Table 145. Bxcan - Register Map And Reset Values - ST STM32F102 Series Reference Manual

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In all configurations:

Bits 31:0 FB[31:0] Filter Bits

Depending on the scale and mode configuration of the filter the function of each register can

differ. For the filter mapping, functions description and mask registers association, refer to

Section 21.4.4: Identifier filtering on page

A Mask/Identifier register in mask mode has the same bit mapping as in identifier list

For the register mapping/addresses of the filter banks please refer to the

bxCAN register map

LOW[2:0] TME[2:0]

Each bit of the register specifies the level of the corresponding bit of the expected

0: Dominant bit is expected

1: Recessive bit is expected

Each bit of the register specifies whether the bit of the associated identifier register

must match with the corresponding bit of the expected identifier or not.

0: Don't care, the bit is not used for the comparison

1: Must match, the bit of the incoming identifier must have the same level has

specified in the corresponding identifier register of the filter.

Table 1 on page 36

for the register boundary addresses.

Controller area network (bxCAN)

Table 145 on

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