ST STM32F102 Series Reference Manual page 249

RM0008
Bit 9 OIS1N: Output Idle state 1 (OC1N output).
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in
TIMx_BKR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output).
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in
TIMx_BKR register).
Bit 7 TI1S: TI1 Selection.
0: The TIMx_CH1 pin is connected to TI1 input.
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[1:0]: Master Mode Selection.
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is
generated by the trigger input (slave mode controller configured in reset mode) then the signal on
TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to
start several timers at the same time or to control a window in which a slave timer is enable. The
Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when
configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is
a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in
TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master timer
can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set
(even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
110: Compare - OC3REF signal is used as trigger output (TRGO).
111: Compare - OC4REF signal is used as trigger output (TRGO).
Bit 3 CCDS: Capture/Compare DMA Selection.
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/Compare Control Update Selection.
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the
COM bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the
COM bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, always read as 0
Bit 0 CCPC: Capture/Compare Preloaded Control.
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only
when COM bit is set.
Note: This bit acts only on channels that have a complementary output.
Advanced-control timers (TIM1&TIM8)
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