Dac Conversion; Figure 40. Data Registers In Single Dac Channel Mode; Figure 41. Data Registers In Dual Dac Channel Mode - ST STM32F102 Series Reference Manual

RM0008

Figure 40. Data registers in single DAC channel mode

●
Dual DAC channels, there are three possibilities:
–
–
–
Depending on the loaded DAC_DHRyyyD register, the data written by the user will be
shifted and stored into the DHR1 and DHR2 (Data Holding Registers, that are internal non-
memory-mapped registers). The DHR1 and DHR2 registers will then be loaded into the
DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an
external event trigger.

Figure 41. Data registers in dual DAC channel mode

11.3.4

DAC conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write on DAC_DHR8Rx, DAC_DHR12Lx,
DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD).
Data stored into the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time of t
the analog output load.
31
8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0]
bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into
DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits)
12-bit left alignment: data for DAC channel1 to be loaded into DAC_DHR12LD
[15:4] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded
into DAC_DHR12LD [31:20] bits (stored into DHR2[11:0] bits)
12-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR12RD
[11:0] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded
into DAC_DHR12LD [27:16] bits (stored into DHR2[11:0] bits)
31
24 15 7
24 15 7
that depends on the power supply voltage and
SETTLING
Digital-to-analog converter (DAC)
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14709
187/690