External Memory Interface Signals; Table 70. Programmable Nor/Psram Access Parameters; Table 71. Nonmuxed I/O Nor Flash - ST STM32F102 Series Reference Manual

RM0008
The programmable memory parameters include access timings (see
for wrap and wait management (for PSRAM and NOR Flash accessed in burst mode).
Table 70.
Parameter
Address
setup
Address hold
Data setup
Bust turn
Clock divide
ratio
Data latency
18.5.1

External memory interface signals

Table 71,
Flash and PSRAM.
Note: Prefix "N". specifies the associated signal as active low.
NOR Flash, nonmultiplexed I/Os
Table 71.
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NWAIT
NOR Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
Programmable NOR/PSRAM access parameters
Function
Duration of the address
setup phase
Duration of the address hold
phase
Duration of the data setup
phase
Duration of the bus
turnaround phase
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Number of clock cycles to
issue to the memory before
the first data of the burst
Table 72 and Table 73
Nonmuxed I/O NOR Flash
FSMC signal name
Flexible static memory controller (FSMC)
Access mode
Asynchronous
Asynchronous,
muxed I/Os
Asynchronous
Asynchronous and
synchronous read
Synchronous
Synchronous
list the signals that are typically used to interface NOR
I/O
O Clock (for synchronous burst)
O Address bus
I/O Bidirectional data bus
O Chip select, x = 1..4
O Output enable
O Write enable
I NOR Flash wait input signal to the FSMC
Table 70) and support
Unit Min.
AHB clock cycle
1
(HCLK)
AHB clock cycle
1
(HCLK)
AHB clock cycle
1
(HCLK)
AHB clock cycle
1
(HCLK)
AHB clock cycle
1
(HCLK)
Memory clock
2
cycle (CLK)
Function
Max.
16
16
256
16
16
17
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