ST STM32F102 Series Reference Manual page 526

Controller area network (bxCAN)
Bit 7 Reserved, forced by hardware to 0.
Bit 6 FOVIE1: FIFO Overrun Interrupt Enable
0: No interrupt when FOVR is set.
1: Interrupt generation when FOVR is set.
Bit 5 FFIE1: FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 4 FMPIE1: FIFO Message Pending Interrupt Enable
0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
Bit 3 FOVIE0: FIFO Overrun Interrupt Enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
Bit 2 FFIE0: FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 1 FMPIE0: FIFO Message Pending Interrupt Enable
0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
Bit 0 TMEIE: Transmit Mailbox Empty Interrupt Enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
Note: refer to
CAN error status register (CAN_ESR)
Address offset: 0x18
Reset value: 0x00
31 30 29
r r r
15 14 13
Bits 31:24 REC[7:0]: Receive Error Counter
The implementing part of the fault confinement mechanism of the CAN protocol. In case of an error
during reception, this counter is incremented by 1 or by 8 depending on the error condition as
defined by the CAN standard. After every successful reception the counter is decremented by 1 or
reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN
controller enters the error passive state.
Bits 23:16 TEC[7:0]: least significant byte of the 9-bit Transmit Error Counter
The implementing part of the fault confinement mechanism of the CAN protocol.
Bits 15:7 Reserved, forced by hardware to 0.
526/690
Section 21.5: bxCAN
28 27 26 25
REC[7:0]
r r r r
12 11 10 9
Reserved
Res.
interrupts.
24 23 22
r r r
8 7 6
LEC[2:0]
rw
21 20 19 18
TEC[7:0]
r r r r
5 4 3 2
Res. BOFF
rw rw r
RM0008
17 16
r r
1 0
EPVF EWGF
r r