Dac Channel1 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12L1); Dac Channel1 8-Bit Right Aligned Data Holding Register; (Dac_Dhr8R1) - ST STM32F102 Series Reference Manual

Digital-to-analog converter (DAC)
11.5.4

DAC channel1 12-bit Left aligned Data Holding Register

(DAC_DHR12L1)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
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Bits 31:16 Reserved.
Bit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit Left aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
Bits 3:0 Reserved.
11.5.5

DAC channel1 8-bit Right aligned Data Holding Register

(DAC_DHR8R1)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:8 Reserved.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit Right aligned data
These bits are written by software which specify 8-bit data for DAC channel1.
200/690
27 26 25
11 10 9
DACC1DHR[11:0]
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27 26 25
11 10 9
Reserved
24 23 22 21
Reserved
8 7 6 5
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24 23 22 21
Reserved
8 7 6 5
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20 19 18 17
4 3 2
Reserved
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20 19 18 17
4 3 2
DACC1DHR[7:0]
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RM0008
16
1 0
16
1 0
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