ST STM32F102 Series Reference Manual page 521

RM0008
Bit 2 ERRI: Error Interrupt
This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the
corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status change
interrupt if the ERRIE bit in the CAN_IER register is set.
This bit is cleared by software.
Bit 1 SLAK: Sleep Acknowledge
This bit is set by hardware and indicates to the software that the CAN hardware is now in Sleep
mode. This bit acknowledges the Sleep mode request from the software (set SLEEP bit in
CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left Sleep mode (to be synchronized on
the CAN bus). To be synchronized the hardware has to monitor a sequence of 11 consecutive
recessive bits on the CAN RX signal.
Note: The process of leaving Sleep mode is triggered when the SLEEP bit in the CAN_MCR register
is cleared. Please refer to the AWUM bit of the CAN_MCR register description for detailed information
for clearing SLEEP bit
Bit 0 INAK: Initialization Acknowledge
This bit is set by hardware and indicates to the software that the CAN hardware is now in
initialization mode. This bit acknowledges the initialization request from the software (set INRQ bit in
CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left the initialization mode (to be
synchronized on the CAN bus). To be synchronized the hardware has to monitor a sequence of 11
consecutive recessive bits on the CAN RX signal.
CAN transmit status register (CAN_TSR)
Address offset: 0x08
Reset value: 0x1C00 0000
31 30 29
LOW2 LOW1 LOW0 TME2
r r r
15 14 13
ABRQ
Reserved
1
rs Res.
Bit 31 LOW2: Lowest Priority Flag for Mailbox 2
This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 2
has the lowest priority.
Bit 30 LOW1: Lowest Priority Flag for Mailbox 1
This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 1
has the lowest priority.
Bit 29 LOW0: Lowest Priority Flag for Mailbox 0
This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 0
has the lowest priority.
Note: The LOW[2:0] bits are set to zero when only one mailbox is pending.
Bit 28 TME2: Transmit Mailbox 2 Empty
This bit is set by hardware when no transmit request is pending for mailbox 2.
28 27 26 25
TME1 TME0 CODE[1:0]
r r r r
12 11 10 9
TERR TXOK
ALST1
1 1
rc_w1 rc_w1 rc_w1
24 23 22 21
ABRQ
Reserved
2
r rs Res.
8 7 6 5
RQCP ABRQ
Reserved
1 0
rc_w1 rs Res.
Controller area network (bxCAN)
20 19 18
TERR
ALST2
2
rc_w1 rc_w1
4 3 2
TERR
ALST0
0
rc_w1 rc_w1
17 16
TXOK RQCP
2 2
rc_w1 rc_w1
1 0
TXOK RQCP
0 0
rc_w1 rc_w1
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