ST STM32F102 Series Reference Manual page 485

RM0008
Bit 2 LP_MODE: Low-power mode
This mode is used when the suspend-mode power constraints require that all static power dissipation
is avoided, except the one required to supply the external pull-up resistor. This condition should be
entered when the application is ready to stop all system clocks, or reduce their frequency in order to
meet the power consumption requirements of the USB suspend condition. The USB activity during
the suspend mode (WKUP event) asynchronously resets this bit (it can also be reset by software).
0: No Low-power mode.
1: Enter Low-power mode.
Bit 1 PDWN: Power down
This bit is used to completely switch off all USB-related analog parts if it is required to completely
disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected
from the transceivers and it cannot be used.
0: Exit Power Down.
1: Enter Power down mode.
Bit 0 FRES: Force USB Reset
0: Clear USB reset.
1: Force a reset of the USB peripheral, exactly like a RESET signalling on the USB. The USB
peripheral is held in RESET state until software clears this bit. A "USB-RESET" interrupt is generated,
if enabled.
USB interrupt status register (USB_ISTR)
Address offset: 0x44
Reset value: 0x0000 0000
15 14 13
PMA
CTR ERR WKUP
OVR
r rc_w0 rc_w0 rc_w0
This register contains the status of all the interrupt sources allowing application software to
determine, which events caused an interrupt request.
The upper part of this register contains single bits, each of them representing a specific
event. These bits are set by the hardware when the related event occurs; if the
corresponding bit in the USB_CNTR register is set, a generic interrupt request is generated.
The interrupt routine, examining each bit, will perform all necessary actions, and finally it will
clear the serviced bits. If any of them is not cleared, the interrupt is considered to be still
pending, and the interrupt line will be kept high again. If several bits are set simultaneously,
only a single interrupt will be generated.
Endpoint transaction completion can be handled in a different way to reduce interrupt
response latency. The CTR bit is set by the hardware as soon as an endpoint successfully
completes a transaction, generating a generic interrupt request if the corresponding bit in
USB_CNTR is set. An endpoint dedicated interrupt condition is activated independently
from the CTRM bit in the USB_CNTR register. Both interrupt conditions remain active until
software clears the pending bit in the corresponding USB_EPnR register (the CTR bit is
actually a read only bit). For endpoint-related interrupts, the software can use the Direction
of Transaction (DIR) and EP_ID read-only bits to identify, which endpoint made the last
interrupt request and called the corresponding interrupt service routine.
The user can choose the relative priority of simultaneously pending USB_ISTR events by
specifying the order in which software checks USB_ISTR bits in an interrupt service routine.
12 11 10 9
SUSP RESET SOF
rc_w0 rc_w0 rc_w0
USB full speed device interface (USB)
8 7 6 5
ESOF Reserved
rc_w0 Res.
4 3 2 1
DIR EP_ID[3:0]
r r r r
0
r
485/690