ST STM32F102 Series Reference Manual page 607

RM0008
Bit 14 DUTY Fast Mode Duty Cycle
0: Fast Mode t
1: Fast Mode t
Bits 13:12 Reserved, forced by hardware to 0.
Bits 11:0 CCR[11:0] Clock Control Register in Fast/Standard mode (Master mode)
Controls the SCL clock in master mode.
Standard Mode or SMBus:
T = CCR * T
high
T = CCR * T
ow
Fast Mode:
If DUTY = 0:
T = CCR * T
high
T = 2 * CCR * T
ow
If DUTY = 1: (to reach 400 kHz)
T = 9 * CCR * T
high
T = 16 * CCR * T
ow
For instance: in standard mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, T
(0x28 <=> 40d x 125 ns = 5000 ns.)
Notes:
1. The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum allowed value
is 0x01
2. t includes the SCLH rising edge
high
3. t includes the SCLH falling edge
low
4. These timings are without filters.
5. The CCR register must be configured only when the I
6. f = a multiple of 10 MHz is required to generate the fast clock at 400 kHz.
CK
/t = 2
low high
/t = 16/9 (see CCR)
low high
PCLK1
PCLK1
PCLK1
PCLK1
PCLK1
PCLK1
= 125 ns so CCR must be programmed with 0x28
PCLK1
Inter-integrated circuit (I
2
C is disabled (PE = 0).
2
C) interface
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