Figure 234. Transfer Sequence Diagram For Master Transmitter - ST STM32F102 Series Reference Manual

Inter-integrated circuit (I
Closing the communication
After writing the last byte to the DR register, the STOP bit is set by software to generate a
Stop condition (see
automatically back to slave mode (M/SL bit cleared).
Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.

Figure 234. Transfer sequence diagram for master transmitter

7-bit Master Transmitter:
S Address
EV5
10-bit Master Transmitter
S
EV5
Legend: S= Start, S
EVx= Event (with interrupt if ITEVFEN=1)
EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2.
EV8_1: TxE=1 shift register empty
EV8: TxE=1 cleared by writing DR register.
EV8_2: TxE=1, BTF = 1 cleared by HW by stop condition
EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.
Master receiver
Following the address transmission and after clearing ADDR, the I
Master Receiver mode. In this mode the interface receives bytes from the SDA line into the
DR register via the internal shift register. After each byte the interface generates in
sequence:
●
An acknowledge pulse if the ACK bit is set
●
The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are
set (see
If the RxNE bit is set and the data in the DR register is not read before the end of the last
data reception, the BTF bit is set by hardware and the interface waits for a read in the DR
register.
Closing the communication
The master sends a NACK for the last byte received from the slave. After receiving this
NACK, the slave releases the control of the SCL and SDA lines. Then the master can send
a Stop/Re-Start condition.
●
In order to generate the non-acknowledge pulse after the last received data byte, the
ACK bit must be cleared just after reading the second last data byte (after second last
RxNE event).
●
In order to generate the Stop/Re-Start condition, software must set the STOP/START
bit just after reading the second last data byte (after the second last RxNE event).
●
In case a single byte is to be received, the Acknowledge disable and the Stop condition
generation are made in EV6.
588/690
2
C) interface
Figure 234
A
EV6 EV8_1
Header A Address
EV9
= Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,
r
Figure 235 Transfer sequencing EV7).
Transfer sequencing EV8_2). The interface goes
Data1 A Data2
EV8 EV8
A Data1
EV6 EV8_1 EV8
A DataN
.....
EV8
A DataN
.....
EV8
2
C interface enters
RM0008
A P
EV8_2
A P
EV8_2