ST STM32F10 Series Application Note
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ST STM32F10 Series Application Note

ST STM32F10 Series Application Note

Hardware development
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AN2586
Application note
STM32F10xxx hardware development:
getting started
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use the STM32F10xxx product family and describes the minimum hardware
resources required to develop an STM32F10xxx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
July 2007
Rev 1
1/23
www.st.com

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  • Page 1 STM32F10xxx product family and describes the minimum hardware resources required to develop an STM32F10xxx application. Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes. July 2007 Rev 1 1/23 www.st.com...

  • Page 2: Table Of Contents

    Contents AN2586 - Application note Contents Power supplies ..........6 Introduction .
  • Page 3 AN2586 - Application note Contents 4.3.4 SWJ debug port connection with Standard JTAG connector ..19 Reference design ......... . 20 Main .
  • Page 4 List of tables AN2586 - Application note List of tables Table 1. Boot modes............. 15 Table 2.
  • Page 5 AN2586 - Application note List of figures List of figures Figure 1. Power supply overview ........... . . 6 Figure 2.

  • Page 6: Power Supplies

    Power supplies AN2586 - Application note Power supplies Introduction The device requires a 2.0 V to 3.6 V operating voltage supply (V ). An embedded regulator is used to supply the internal 1.8 V digital power. The real-time clock (RTC) and backup registers can be powered from the V voltage when the main V supply is powered off.

  • Page 7: Battery Backup

    AN2586 - Application note Power supplies On packages with 64 pins or less The V and V pins are not available, they are internally connected to the ADC REF+ REF- voltage supply (V ) and ground (V 1.1.2 Battery backup To retain the content of the Backup registers when V is turned off, the V pin can be...

  • Page 8: Reset & Power Supply Supervisor

    Power supplies AN2586 - Application note Figure 2. Power supply scheme STM32F10xxx REF+ Battery 10 nF + 1 µF (note 1) 10 nF + 1 µF 5 × 100 nF DD 1/2/3/4/5 + 1 × 10 µF REF– SS 1/2/3/4/5 ai14363 1.

  • Page 9: Programmable Voltage Detector (Pvd)

    AN2586 - Application note Power supplies 1.3.2 Programmable voltage detector (PVD) You can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate whether V is higher or lower than the PVD threshold.

  • Page 10: Figure 5. Reset Circuit

    Power supplies AN2586 - Application note Figure 5. Reset circuit V DD External reset circuit R ON NRST System nreset Filter 0.1 µF WWDG reset Pulse IWDG reset generator POR/PDR reset (min 20 µs) Software reset Low-power management reset ai14366 10/23...

  • Page 11: Clocks

    AN2586 - Application note Clocks Clocks Three different clock sources can be used to drive the system clock (SYSCLK): HSI oscillator clock (high speed internal clock signal) HSE oscillator clock (high speed external clock signal) PLL clock The devices have two secondary clock sources: 32 kHz low speed internal RC (LSI RC) that drives the independent watchdog and, optionally, the RTC used for Auto Wake-up from the Stop/Standby modes.

  • Page 12: Hse Osc Clock

    Clocks AN2586 - Application note HSE OSC clock The high speed external clock signal (HSE) can be generated from two possible clock sources: HSE external crystal/ceramic resonator (see Figure HSE user external clock (see Figure Figure 7. External clock Figure 8. Crystal/ceramic resonators Hardware configuration STM32F10xxx...

  • Page 13: Lse Osc Clock

    AN2586 - Application note Clocks LSE OSC clock The low-speed external clock signal (LSE) can be generated from two possible clock sources: LSE external crystal/ceramic resonator (see Figure LSE user external clock (see Figure Figure 9. External clock Figure 10. Crystal/ceramic resonators Hardware configuration STM32F10xxx Hardware configuration...

  • Page 14: Clock Security System (Css)

    HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too. For details, see reference manual UM0306 available from the STMicroelectronics website www.st.com. 14/23...

  • Page 15: Boot Configuration

    AN2586 - Application note Boot configuration Boot configuration Boot mode selection In the STM32F10xxx, three different boot modes can be selected by means of the BOOT[1:0] pins as shown in Table Table 1. Boot modes BOOT mode selection pins Boot mode Aliasing BOOT1 BOOT0...

  • Page 16: Embedded Boot Loader Mode

    The Embedded Boot Loader mode is used to reprogram the Flash memory using one of the serial interfaces (typically a UART). This program is located in the system memory and is programmed by ST during production. For details, refer to the STM32F10xxx Flash programming manual, PM0042, available from the STMicroelectronics website, www.st.com.

  • Page 17: Debug Management

    AN2586 - Application note Debug management Debug management Introduction The Host/Target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool. Figure 12 shows the connection of the host to the STM3210B-EVAL board.

  • Page 18: Flexible Swj-Dp Pin Assignment

    Table 3 shows the different possibilities to release some pins. For more details, see the STM32F10xxx reference manual, UM0306, available from the STMicroelectronics website www.st.com. 4.3.3 Internal pull-up and pull-down on JTAG pins The JTAG input pins must not be floating since they are directly connected to flip-flops to control the debug mode features.

  • Page 19: Figure 13. Jtag Connector Implementation

    AN2586 - Application note Debug management To avoid any uncontrolled I/O levels, the STM32F10xxx embeds internal pull-up and pull- down resistors on JTAG input pins: JNTRST: Internal pull-up JTDI: Internal pull-up JTMS/SWDIO: Internal pull-up TCK/SWCLK: Internal pull-down Once a JTAG I/O is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state: JNTRST: Input pull-up JTDI: Input pull-up...
  • Page 20 Reference design AN2586 - Application note Reference design Main The reference design shown in Figure 14, is based on the STM32F10xxx, a highly ™ integrated microcontroller running at 72 MHz, that combines the new Cortex -M3 32-bit RISC CPU core with 128 Kbytes of embedded Flash memory and up to 20 Kbytes of high speed SRAM 5.1.1 Clock...

  • Page 21: Figure 14. Stm32F10Xxx Microcontroller Reference Schematic

    AN2586 - Application note Reference design Figure 14. STM32F10xxx microcontroller reference schematic 21/23...

  • Page 22: Table 4

    Revision history AN2586 - Application note Revision history Table 4. Document revision history Date Revision Changes 12-Jul-2007 Initial release. 22/23...
  • Page 23 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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