Timx Registers; Control Register 1 (Timx_Cr1) - ST STM32F102 Series Reference Manual

General-purpose timer (TIMx)
13.4

TIMx registers

Refer to
13.4.1

Control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Reserved
Bits 15:10 Reserved, always read as 0
Bits 9:8 CKD: Clock Division.
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling
clock used by the digital filters (ETR, TIx),
00: t
DTS
01: t
DTS
10: t
DTS
11: Reserved
Bit 7 ARPE: Auto-Reload Preload enable.
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:5 CMS: Center-aligned Mode Selection.
00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only
when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only
when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both
when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the
counter is enabled (CEN=1)
Bit 4 DIR: Direction.
0: Counter used as upcounter.
1: Counter used as downcounter.
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
Bit 3 OPM: One Pulse Mode.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN).
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Section 1.1 on page 32
12 11 10 9
CKD[1:0]
rw
= t
CK_INT
= 2 × t
CK_INT
= 4 × t
CK_INT
for a list of abbreviations used in register descriptions.
8 7 6
ARPE CMS
rw rw rw
5 4 3 2
DIR OPM URS
rw rw rw rw
RM0008
1 0
UDIS CEN
rw rw