Af Remap And Debug I/O Configuration Register (Afio_Mapr) - ST STM32F102 Series Reference Manual

RM0008
7.4.2

AF remap and debug I/O configuration register (AFIO_MAPR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Reserved
Res.
15 14 13
PD01_ CAN_REMAP TIM4_
REMAP [1:0] REMAP
rw rw rw
Bits 31:27 Reserved
Bits 26:24 SWJ_CFG[2:0] Serial wire JTAG configuration
These bits are write-only (when read, the value is undefined). They are used to configure the SWJ
and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to
the Cortex debug port. The default state after reset is SWJ ON without trace. This allows JTAG or
SW mode to be enabled by sending a specific sequence on the JTMS / JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
Bits 23:21 Reserved
Bits 20 ADC2_ETRGREG_REMAP ADC 2 external trigger regular conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger
regular conversion. When this bit is reset, the ADC2 external trigger regular conversion is
connected to EXTI11. When this bit is set, the ADC2 external event regular conversion is
connected to TIM8_TRGO.
Bits 19 ADC2_ETRGINJ_REMAP ADC 2 external trigger injected conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger
injected conversion. When this bit is reset, the ADC2 external trigger injected conversion is
connected to EXTI15. When this bit is set, the ADC2 external event injected conversion is
connected to TIM8_Channel4.
Bits 18 ADC1_ETRGREG_REMAP ADC 1 external trigger regular conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC1
External trigger regular conversion. When reset the ADC1 External trigger regular conversion is
connected to EXTI11. When set the ADC1 External Event regular conversion is connected to TIM8
TRGO.
Bits 17 ADC1_ETRGINJ_REMAP ADC 1 External trigger injected conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC1
External trigger injected conversion. When reset the ADC1 External trigger injected conversion is
connected to EXTI15. When set the ADC1 External Event injected conversion is connected to TIM8
Channel4.
Bits 16 TIM5CH4_IREMAP TIM5 channel4 internal remap
Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the
timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to TIM5_CH4
input for calibration purpose.
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
28 27 26 25
SWJ_
CFG[2:0]
w w
12 11 10 9
TIM3_REMAP TIM2_REMAP
[1:0]
rw rw rw rw
24 23 22
Reserved
w Res.
8 7 6
TIM1_REMAP
[1:0] [1:0]
rw rw rw
21 20 19 18
ADC2_ ADC2_ ADC1_
ETRGR ETRGIN ETRGR
EG_RE J_REM EG_RE
MAP AP MAP
rw rw rw
5 4 3 2
USART USART
USART3_
2_ 1_
REMAP[1:0]
REMAP REMAP
rw rw rw rw
17 16
ADC1_
TIM5CH
ETRGIN
4_IREM
J_REM
AP
AP
rw rw
1 0
I2C1_ SPI1_
REMAP REMAP
rw rw
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