Ahb Peripheral Clock Enable Register (Rcc_Ahbenr) - ST STM32F102 Series Reference Manual

RM0008
Bit 5 TIM7RST Timer 7 reset
Set and reset by software.
0: No effect
1: Reset timer 7
Bit 4 TIM6RST Timer 6 reset
Set and reset by software.
0: No effect
1: Reset timer 6
Bit 3 TIM5RST Timer 5 reset
Set and reset by software.
0: No effect
1: Reset timer 5
Bit 2 TIM4RST Timer 4 reset
Set and reset by software.
0: No effect
1: Reset timer 4
Bit 1 TIM3RST Timer 3 reset
Set and reset by software.
0: No effect
1: Reset timer 3
Bit 0 TIM2RST Timer 2 reset
Set and reset by software.
0: No effect
1: Reset timer 2
6.3.6

AHB Peripheral Clock enable register (RCC_AHBENR)

Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
Reserved
Res.
Bits 31:11 Reserved, always read as 0.
Bit 10 SDIOEN SDIO clock enable
Set and reset by software.
0: SDIO clock disabled
1: SDIO clock enabled
Bits 9 Reserved, always read as 0.
28 27 26 25
12 11 10 9
SDIO
Res.
EN
rw Res.
24 23 22 21
Reserved
8 7 6 5
FSMC
CRCE
Res. Res.
N
EN
rw Res. rw Res.
Reset and clock control (RCC)
20 19 18
4 3 2
FLITF SRAM DMA2
Res.
EN EN EN
rw Res. rw
17 16
1 0
DMA1
EN
rw rw
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