Table 76. Fsmc_Tcrx Bit Fields; Figure 161. Modea Read Accesses - ST STM32F102 Series Reference Manual

Flexible static memory controller (FSMC)
Table 76.
Bit
number
31-16
15-8
7-4
3-0
Mode A - SRAM/PSRAM (CRAM) OE toggling

Figure 161. ModeA read accesses

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FSMC_TCRx bit fields
Bit name
0x0000
Duration of the second access phase (DATAST+1 HCLK cycles) for
DATAST write accesses, DATAST+3 HCLK cycles for read accesses). This
value cannot be 0 (minimum is 1)
0x0
ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles).
A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
D[15:0]
(ADDSET +1)
Value to set
Memory transaction
(DATAST + 1)
HCLK cycles HCLK cycles
data driven
by memory
2 HCLK
cycles
Data sampled Data strobe
RM0008
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