ST STM32F102 Series Reference Manual page 79

RM0008
Bits 31:26 Reserved, always read as 0.
Bits 26:24 MCO Microcontroller clock output
Set and reset by software.
0xx: No clock
100: System clock selected
101: Internal 8 MHz RC oscillator clock selected
110: External 1-25 MHz oscillator clock selected
111: PLL clock divided by 2 selected
Note: This clock output could have some truncated cycle at startup or during MCO clock source
switching.
When the System Clock is selected to output onto MCO, make sure that this clock does not
exceed 50 MHz (the maximum I/O speed).
Bit 22 USBPRE USB prescaler
Set and reset by software to generate 48 MHz USB clock. This bit must be valid before enabling the
USB clock in the RCC_APB1ENR register. This bit can't be reset if the USB clock is enabled.
0: PLL clock is divided by 1.5
1: PLL clock is not divided
Bits 21:18 PLLMUL PLL multiplication factor
These bits are written by software to define the PLL multiplication factor. These bits can be written
only when PLL is disabled.
Caution: The PLL output frequency must not exceed 72 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
Bit 17 PLLXTPRE HSE divider for PLL entry
Set and reset by software to divide HSE before PLL entry. This bit can be written only when PLL is
disabled.
0: HSE clock not divided
1: HSE clock divided by 2
Bit 16 PLLSRC PLL entry clock source
Set and reset by software to select PLL clock source. This bit can be written only when PLL is
disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock
Reset and clock control (RCC)
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