Figure 69. Ti2 External Clock Connection Example; Figure 115. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32F102 Series Reference Manual

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General-purpose timer (TIMx)

Figure 115. Control circuit in normal mode, internal clock divided by 1

Counter clock = CK_CNT = CK_PSC
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.
Figure 116. TI2 external clock connection example
For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= '01' in the
TIMx_CCMR1 register.
2.
Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
Note:
The capture prescaler is not used for triggering, so you don't need to configure it.
3.
Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4.
Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5.
Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.
6.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
286/690
CK_INT
CEN=CNT_EN
CNT_INIT
COUNTER REGISTER
TI2
Edge
Filter
Detector
TI2F_Falling
ICF[3:0]
TIMx_CCMR1
UG
31
32 33 34 35 36
TIMx_SMCR
TS[2:0]
ITRx
001
TI1F_ED
100
TI1FP1
101
TI2F_Rising
0
TI2FP2
110
1
ETRF
111
CC2P
TIMx_CCER
00
01 02 03 04 05 06 07
TI2F
or
or
TI1F
or
encoder
mode
external clock
TRGI
mode 1
ETRF
external clock
mode 2
CK_INT
internal clock
mode
(internal clock)
ECE
SMS[2:0]
TIMx_SMCR
RM0008
CK_PSC

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