Dac Software Trigger Register (Dac_Swtrigr); Dac Channel1 12-Bit Right-Aligned Data Holding Register; (Dac_Dhr12R1) - ST STM32F102 Series Reference Manual

RM0008
11.5.2

DAC Software Trigger Register (DAC_SWTRIGR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:2 Reserved.
Bit 1 SWTRIG2: DAC channel2 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value
is loaded to the DAC_DOR2 register.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value
is loaded to the DAC_DOR1 register.
11.5.3

DAC channel1 12-bit Right-aligned Data Holding Register

(DAC_DHR12R1)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved.
Bit 11:0 DACC1DHR[11:0]: DAC channel1 12-bit Right aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
27 26 25 24
Reserved
11 10 9 8
Reserved
27 26 25 24
Reserved
11 10 9 8
rw rw rw rw
Digital-to-analog converter (DAC)
23 22 21 20
7 6 5 4
23 22 21 20
7 6 5 4
DACC1DHR[11:0]
rw rw rw rw
19 18 17 16
3 2 1 0
SWTRI SWTRI
G2 G1
w w
19 18 17 16
3 2 1 0
rw rw rw rw
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