ST STM32F102 Series Reference Manual page 92

Reset and clock control (RCC)
Bit 14 SPI2EN SPI 2 clock enable
Set and reset by software.
0: SPI 2 clock disabled
1: SPI 2 clock enabled
Bits 13:12 Reserved, always read as 0.
Bit 11 WWDGEN Window Watchdog clock enable
Set and reset by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:6 Reserved, always read as 0.
Bit 5 TIM7EN Timer 7 clock enable
Set and reset by software.
0: Timer 7 clock disabled
1: Timer 7 clock enabled
Bit 4 TIM6EN Timer 6 clock enable
Set and reset by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled
Bit 3 TIM5EN Timer 5 clock enable
Set and reset by software.
0: Timer 5 clock disabled
1: Timer 5 clock enabled
Bit 2 TIM4EN Timer 4 clock enable
Set and reset by software.
0: Timer 4 clock disabled
1: Timer 4 clock enabled
Bit 1 TIM3EN Timer 3 clock enable
Set and reset by software.
0: Timer 3 clock disabled
1: Timer 3 clock enabled
Bit 0 TIM2EN Timer 2 clock enable
Set and reset by software.
0: Timer 2 clock disabled
1: Timer 2 clock enabled
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RM0008