Error Conditions; Figure 235. Transfer Sequence Diagram For Master Receiver - ST STM32F102 Series Reference Manual

RM0008
After the Stop condition generation, the interface goes automatically back to slave mode
(M/SL bit cleared).

Figure 235. Transfer sequence diagram for master receiver

7-bit Master Receiver:
S Address
EV5
10-bit Master Receiver
S
EV5
Legend: S= Start, S
EVx= Event (with interrupt if ITEVFEN=1)
EV5: SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2. In 10-bit master receiver mode, this se-
quence should be followed by writing CR2 with START = 1.
EV7: RxNE=1 cleared by reading DR register.
EV7_1: RxNE=1 cleared by reading DR register, program ACK=0 and STOP request
EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.
23.3.4

Error conditions

The following are the error conditions which may cause communication to fail.
Bus error (BERR)
This error occurs when the I
transfer. In this case,
●
The BERR bit is set and an interrupt is generated if the ITERREN bit is set
● In case of Slave: data is discarded and the lines are released by hardware:
–
–
Acknowledge failure (AF)
This error occurs when the interface detects a non-acknowledge bit. In this case,
● The AF bit is set and an interrupt is generated if the ITERREN bit is set
●
A transmitter which receives a NACK must reset the communication:
–
–
A Data1
EV6
Header A Address
EV9
S
r
EV5
= Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,
r
2
C interface detects a Stop or a Start condition during a byte
in case of misplaced start, the slave considers it is a restart and waits for address,
or stop condition.
in case of misplaced stop, the slave reacts like for a stop condition and the lines
are released by hardware.
If Slave: lines are released by hardware
If Master: a Stop condition must be generated by software
Inter-integrated circuit (I
A Data2 A
EV7 EV7
A
EV6
Header A Data1
EV6
DataN NA
.....
EV7_1 EV7
A DataN
.....
EV7 EV7_1
2
C) interface
P
NA P
EV7
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