External Memory Interface Signals; Table 95. Programmable Nand/Pc Card Access Parameters; Table 96. 8-Bit Nand Flash - ST STM32F102 Series Reference Manual

RM0008
Table 95.
Parameter
Memory setup
time
Memory wait
Memory hold
Memory
databus high-Z
18.6.1

External memory interface signals

The following tables list the signals that are typically used to interface NAND Flash and PC
Card.
Note: Prefix "N". specifies the associated signal as active low.
8-bit NAND Flash
t
Table 96.
FSMC signal name
A[17]
A[16]
D[7:0]
NOE(= NRE)
NWE
NWAIT
There is no theoretical capacity limitation as the FSMC can manage as many address
cycles as needed.
Programmable NAND/PC Card access parameters
Function
Number of clock cycles (HCLK)
to set up the address before the
command assertion
Minimum duration (HCLK clock
cycles) of the command assertion
Number of clock cycles (HCLK)
to hold the address (and the data
in case of a write access) after
the command de-assertion
Number of clock cycles (HCLK)
during which the databus is kept
in high-Z state after the start of a
write access
8-bit NAND Flash
I/O
O NAND Flash address latch enable (ALE) signal
O NAND Flash command latch enable (CLE) signal
I/O 8-bit multiplexed, bidirectional address/data bus
O Output enable (memory signal name: read enable, NRE)
O Write enable
I NAND Flash ready/busy input signal to the FSMC
Flexible static memory controller (FSMC)
Access mode
AHB clock cycle
Read/Write
(HCLK)
AHB clock cycle
Read/Write
(HCLK)
AHB clock cycle
Read/Write
(HCLK)
AHB clock cycle
Write
(HCLK)
Function
Unit Min. Max.
1 256
1 256
1 255
0 255
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