Rtc Registers; Rtc Control Register High (Rtc_Crh) - ST STM32F102 Series Reference Manual

RM0008
15.4

RTC registers

Refer to
15.4.1

RTC control register high (RTC_CRH)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Bits 15:3 Reserved, forced by hardware to 0.
Bit 2 OWIE: OverfloW Interrupt Enable
0: Overflow interrupt is masked.
1: Overflow interrupt is enabled.
Bit 1 ALRIE: Alarm Interrupt Enable
0: Alarm interrupt is masked.
1: Alarm interrupt is enabled.
Bit 0 SECIE: Second Interrupt Enable
0: Second interrupt is masked.
1: Second interrupt is enabled.
These bits are used to mask interrupt requests. Note that at reset all interrupts are disabled,
so it is possible to write to the RTC registers to ensure that no interrupt requests are pending
after initialization. It is not possible to write to the RTC_CRH register when the peripheral is
completing a previous write operation (flagged by RTOFF=0, see
345).
The RTC functions are controlled by this control register. Some bits must be written using a
specific configuration procedure (see
Section 1.1 on page 32
12 11 10 9
Reserved
for a list of abbreviations used in register descriptions.
8 7 6
Configuration procedure:).
Real-time clock (RTC)
5 4 3 2
OWIE
rw
Section 15.3.4 on page
1 0
ALRIE SECIE
rw rw
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