Rising Trigger Selection Register (Exti_Rtsr); Falling Trigger Selection Register (Exti_Ftsr) - ST STM32F102 Series Reference Manual

RM0008
8.3.3

Rising trigger selection register (EXTI_RTSR)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
15 14 13
TR15 TR14 TR13 TR12
rw rw rw
Bits 31:19 Reserved, must be kept at reset value (0).
Bits 18:0 TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines.
If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
8.3.4

Falling trigger selection register (EXTI_FTSR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
15 14 13
TR15 TR14 TR13 TR12
rw rw rw
Bits 31:19 Reserved, must be kept at reset value (0).
Bits 18:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines.
If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
28 27 26 25
Reserved
Res.
12 11 10 9
TR11 TR10 TR9
rw rw rw rw
28 27 26 25
Reserved
Res.
12 11 10 9
TR11 TR10 TR9
rw rw rw rw
24 23 22 21
8 7 6 5
TR8 TR7 TR6 TR5
rw rw rw rw
24 23 22 21
8 7 6 5
TR8 TR7 TR6 TR5
rw rw rw rw
Interrupts and events
20 19 18 17
TR18 TR17
rw rw
4 3 2 1
TR4 TR3 TR2 TR1
rw rw rw rw
20 19 18 17
TR18 TR17
rw rw
4 3 2 1
TR4 TR3 TR2 TR1
rw rw rw rw
16
TR16
rw
0
TR0
rw
16
TR16
rw
0
TR0
rw
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